The Strangest Secret in the World

What is your new year 2010 resolution? No idea? No plan? In loss?
Then, this video clip below is the best gift to you for 2010.....

The Strangest Secret in the World

Short Trip to Malacca

Ping-pong sized chicken rice ball

We went to Malacca during the last weekend, but ended up we were trapped in the traffic for few hours in nouth-south highway and it rained heavily. After taking the exit to Ayer Keroh, we were trapped again along in the Ayer Keroh road toward the city centre for few hours. Furthermore, one of the road was in flood, causing a massive jam. What a bad day to visit Malacca during holiday. The heavy traffic, I believe, was also due to the Malacca has been promoted as a World Heritage city.

The machine to churn out the rice ball

When we were about to reach near to the red house, the road was closed. We finally gave up and just stopped to have our dinner at one of the chicken rice shop which also serve chicken rice ball. The shop name is called Famosa Chicken Rice Ball 古城鸡饭粒. Initially we planned to have the chicken rice ball at the famous shop called Hoe Kee Chicken Rice ball in Jonker Street, but we didnt make it.

My brother and his family... where was Jing Hong?

Parents and Jing Hong

My family.. Jing Yi was excited seeing the food

Savouring..

Birthday Party

My wife and bb attended a cousin birthday party

Lovely Princess Happy Birthday Cake

Happy Smiling Face or Paw?

Birthday party.... guess who was the birthday girl?

When Jing Yi meet Xin Hui.... eye contacting?

BB was so happy and thrilled at the party

The party held at a club house in PJ.

But I didnt attend the party.... :p

The Wedding Finger

The Wedding Finger

EVER WONDERED WHY WEDDING RINGS SHOULD BE ON YOUR FOURTH FINGER AND NO WHERE ELSE? READ AND TRY THIS, YOU WON'T BELIEVE IT

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Why should the wedding ring be worn on the fourth finger?

There is a beautiful and convincing explanation given by the Chinese .....

The thumb represents your Parents.
The second (index) finger represents your Siblings.
The middle finger represents you.
The fourth (ring) finger represents your Life Partner.
The last (little) finger represents your children.


First, open your palms (face to face),bend the middle fingers and hold them together,back to back.

Second, open and hold the remaining three fingersand the thumb - tip to tip.
(As shown in the figure below):


Now, try to separate your thumbs (representing the parents). They will open, because your parents are not destined to live with you lifelong, and have to leave you sooner or later.

Please join your thumbs as before and separate your Index fingers (representing siblings). They will also open, because your brothers and sisters will have their own families and will have to lead their separate lives.

Now rejoin the index fingers and separate your little fingers (representing your children). They will open too, because the children also will get married and settle down on their own some day.

Finally, rejoin your little fingers, and try to separate your ring fingers (representing your spouse). You'll be surprised to see that you just CANNOT, because husband & wife have to remain together all their lives - through thick and thin!!

Mid Autumn 09

My Parent Mid Autumn Gathering

Take II

Lantern Decoration.

My parents and relatives

China Town & Clarke Quay

China Town, selling miscellaneous stuff, souvenir, cloths.

During Deepavali festival, my friend (Yong) and I went to visit China Town in Singapore. It was the first time I came to here after studying in NTU. We took MRT from Boon Lay to Outram Park and walked to China Town. I found that it is very similar to a Petaling Street in Kuala Lumpur. Over there, it sells miscellaneous stuff, like souvenir, cloths, food and beverage and etc. Most of items are from China.



There has one street selling variety food, like Malaysia/Singapore style food, China food, Vietnam food, western food. There are plenty of choice. China food look delicious, but we decided to try Vietnam food. I order vietnam style beef noodle. In my opinion, it was so so only. Besides this, I also found there was another street serving China sytle steam boat. The Xi Chuan steam boat looked good but would it be too hot and spicy to me?

After that we walked toward to Boat Quay, located near Singapore River. It was a good place to view night view, seeing the vibrancy of Singapore and skyscraper , some historical buildings. Besides this, there are many seafood restaurants, the famous food is black pepper crab. Next time I need to try out and see.

Numerous Seafood restaurant along the Boat Quay

Do you dare to try this? Whampoa Garden - GMax2000

Pubs & bars in Clarke Quay

Night life in Clarke Quay

Dont miss this funny Turkey ice-cream tricks

Intel Takes 32 nm PMOS to Record Levels

source from http://www.semiconductor.net/article/439536-Intel_Takes_32_nm_PMOS_to_Record_Levels.php?nid=3572&source=title&rid=8462992

At IEDM, Intel manager Paul Packen said Intel's flagship 32 nm technology achieved record drive current levels, with the PMOS transistor showing a 35% drive current improvement over the 45 nm PMOS device. "For the first time, linear drive currents on the PMOS have overtaken NMOS," he said. The sharp gain in PMOS performance comes partly by adding germanium to the SiGe stressors, and from the replacement-gate process.

David Lammers, News Editor -- Semiconductor International, 12/10/2009

Intel Corp. presented details on its 32 nm logic technology at the International Electron Devices Meeting (IEDM), reporting that its fourth-generation strain techniques have boosted the PMOS performance to a historic point. "For the first time, linear drive currents on the PMOS have overtaken NMOS," said Paul Packan, 32 and 15 nm technology programs manager.

For the oft-quoted saturated drive current, the 32 nm NMOS value remains higher, at 1.62 mA/μm I_dsatdlin) reached 0.24 mA/μm, a 35% improvement over the 45 nm PMOS transistor. The NMOS device I_dlin gained a 20% improvement, partly from a raised source-drain architecture, reaching a linear drive current of 0.231 mA/μm. Linear drive current is important because transistors rarely get to full saturation, making I_dlin a meaningful metric for real-world device operation. compared with 1.37 mA/μm for the 32 nm PMOS transistor. Packan said the PMOS linear drive current (l

Intel used a raised source-drain for its 32 nm NMOS transistors.

With NMOS and PMOS now in rough parity, designers can adjust the size of the PMOS transistors to their needs, said Mark Bohr, a senior fellow at Intel. "For many generations, there was a 2:1 ratio between the NMOS and PMOS," largely caused by inherently different mobilities between electrons and holes. "At the 32 nm generation, our saturation and linear drive currents are closer to being matched; we are getting very close." That means for the Westmere processor Intel designers could create circuits with smaller PMOS transistors in some cases, Bohr said.

The sharp gain in PMOS performance comes partly by adding more germanium to the SiGe stressors, to a 40% level. Also, "we are moving the SiGe closer to the channel at the 32 nm generation, which is challenging at these dimensions," Bohr said.

The replacement gate technique adds another boost, rivaling that of the SiGe stressors. Before high-k/metal gate technology was introduced, the polysilicon electrode was neutral in terms of strain on the PMOS channel. With the replacement gate, or gate-last, technology, removal of the sacrificial gate allows the SiGe stress regions to exert a stronger tensile strain on the channel, reaching 2 GPa.

For the NMOS, the raised source and drain reduces resistance, "helping to mitigate the pitch scaling issues," Packan said. By moving transistors closer together, there is less room for stress regions. Though in previous interviews Bohr has not been positive about the value of SiC stressors on the NMOS channel, he declined to comment on whether Intel is using SiC at the 32 nm node.

Although Intel remains on a Moore's Law pace in terms of contacted gate pitch scaling, with a 112.5 nm pitch, shrinking is no longer delivering the speed improvements seen in past generations, Packan said. With smaller dimensions, less material can be deposited to add strain. And threshold voltages have crept up slightly in recent years at the same I_off levels.

Without increased strain, CMOS transistors would be losing performance as the gate length scales.

"Traditional scaling is losing steam," Packan told the standing-room-only Wednesday IEDM session on leading-edge CMOS. He estimated that were it not for the additional benefits of higher strain, performance actually would have declined for the 32 nm transistors. One reason, Bohr said, is that to counter short channel effects in the aggressively scaled gates the channel must receive higher dopant levels, causing threshold voltages to rise and slowing down the transistor.

"We need a new paradigm for performance improvement," Packan said.

Though several participants at IEDM said CMOS scaling is likely to slow to a three-year pace, Bohr said Intel plans to stay on a two-year cadence. The Westmere processors are shipping now from two Intel fabs to computer vendors, and the 22 nm technology is on pace to ship two years later. Not only does Intel want to remain ahead of its MPU competition, its computer customers need faster MPUs every two years so they can sell new systems to their customers, he said.

How a chip is made (from sand to silicon)

source from -> http://apcmag.com/picture-gallery-how-a-chip-is-made.htm?page=1

    

It starts with sand.

With about 25% (mass) Silicon is – after Oxygen – the second most frequent chemical element in the earth’s crust. Sand – especially Quartz - has high percentages of Silicon in the form of Silicon dioxide (SiO2) and is the base ingredient for semiconductor manufacturing.

Melted Silicon

scale: wafer level (~300mm/ 12 inch)
Silicon is purified in multiple steps to finally reach semiconductor manufacturing quality which is called Electronic Grade Silicon. Electronic Grade Silicon may only have one alien atom every one billion Silicon atoms. In this picture you can see how one big crystal is grown from the purified silicon melt. The resulting mono crystal is called Ingot.

Mono-crystal Silicon Ingot

scale: wafer level (~300mm/ 12 inch)
An ingot has been produced from Electronic Grade Silicon. One ingot weights about 100 kilograms (=220 pounds) and has a Silicon purity of 99.9999%.

Ingot Slicing

scale: wafer level (~300mm / 12 inch)
The Ingot is cut into individual silicon discs called wafers.

Wafer

scale: wafer level (~300mm/ 12 inch)
The wafers are polished until they have flawless, mirror-smooth surfaces. Intel buys those manufacturing ready wafers from third party companies. Intel’s highly advanced 45nm High-K/Metal Gate process uses wafers with a diameter of 300 millimeter (~12 inches). When Intel first began making chips, the company printed circuits on 2-inch (50mm) wafers. Now the company uses 300mm wafers, resulting in decreased costs per chip.

Applying Photo Resist

scale: wafer level (~300mm / 12 inch)
The liquid (blue here) that’s poured onto the wafer while it spins is a photo resist finish similar as the one known from film photography. The wafer spins during this step to allow very thin and even application of this photo resist layer.

Exposure

scale: wafer level (~300mm / 12 inch)
The photo resist finish is exposed to ultra violet (UV) light. The chemical reaction triggered by that process step is similar to what happens to film material in a film camera the moment you press the shutter button. The photo resist finish that’s exposed to UV light will become soluble. The exposure is done using masks that act like stencils in this process step. When used with UV light, masks create the various circuit patterns on each layer of the microprocessor. A lens (middle) reduces the mask’s image. So what gets printed on the wafer is typically four times smaller linearly than the mask’s pattern.

Exposure

scale: transistor level (~50-200nm)
Although usually hundreds of microprocessors are built on a single wafer, this picture story will only focus on a small piece of a microprocessor from now on –on a transistor or parts thereof. A transistor acts as a switch, controlling the flow of electrical current in a computer chip. Intel researchers have developed transistors so small that about 30 million of them could fit on the head of a pin.

Washing off of Photo Resist

scale: transistor level (~50-200nm)
The gooey photo resist is completely dissolved by a solvent. This reveals a pattern of photo resist made by the mask.

Etching

scale: transistor level (~50-200nm)
The photo resist is protecting material that should not be etched away. Revealed material will be etched away with chemicals.

Removing Photo Resist

scale: transistor level (~50-200nm)
After the etching the photo resist is removed and the desired shape becomes visible.

Applying Photo Resist

scale: transistor level (~50-200nm)
There’s photo resist (blue color) applied, exposed and exposed photo resist is being washed off before the next step. The photo resist will protect material that should not get ions implanted.

Ion Implantation

scale: transistor level (~50-200nm)
Through a process called ion implantation (one form of a process called doping), the exposed areas of the silicon wafer are bombarded with various chemical impurities called Ions. Ions are implanted in the silicon wafer to alter the way silicon in these areas conducts electricity. Ions are shot onto the surface of the wafer at very high speed. An electrical field accelerates the ions to a speed of over 300,000 km/h (~185,000 mph)

Removing Photo Resist

scale: transistor level (~50-200nm)
After the ion implantation the photo resist will be removed and the material that should have been doped (green) has alien atoms implanted now (notice slight variations in color)

Ready Transistor

scale: transistor level (~50-200nm)
This transistor is close to being finished. Three holes have been etched into the insulation layer (magenta color) above the transistor. These three holes will be filled with copper which will make up the connections to other transistors.

Electroplating

scale: transistor level (~50-200nm)
The wafers are put into a copper sulphate solution as this stage. The copper ions are deposited onto the transistor thru a process called electroplating. The copper ions travel from the positive terminal (anode) to the negative terminal (cathode) which is represented by the wafer.

After Electroplating

scale: transistor level (~50-200nm)
On the wafer surface the copper ions settle as a thin layer of copper.

Polishing

scale: transistor level (~50-200nm)
The excess material is polished off.

Metal Layers

scale: transistor level (six transistors combined ~500nm)
Multiple metal layers are created to interconnect (think: wires) in between the various transistors. How these connections have to be "wired" is determined by the architecture and design teams that develop the functionality of the respective processor (e.g. Intel Core i7 Processor ). While computer chips look extremely flat, they may actually have over 20 layers to form complex circuitry. If you look at a magnified view of a chip, you will see an intricate network of circuit lines and transistors that look like a futuristic, multi-layered highway system.


scale: die level (~10mm / ~0.5 inch)
This fraction of a ready wafer is being put to a first functionality test. In this stage test patterns are fed into every single chip and the response from the chip monitored and compared to "the right answer".

Wafer Sort Test

Wafer Slicing

scale: wafer level (~300mm / 12 inch)
The wafer is cut into pieces (called dies).

Discarding faulty dies

scale: wafer level (~300mm / 12 inch)
The dies that responded with the right answer to the test pattern will be put forward for the next step (packaging).

Individual Die

scale: die level (~10mm / ~0.5 inch)
This is an individual die which has been cut out in the previous step (slicing). The die shown here is a die of an Intel Core i7 Processor .

Packaging

scale: package level (~20mm / ~1 inch)
The substrate, the die and the heatspreader are put together to form a completed processor. The green substrate builds the electrical and mechanical interface for the processor to interact with the rest of the PC system. The silver heatspreader is a thermal interface where a cooling solution will be put on to. This will keep the processor cool during operation.

Processor

scale: package level (~20mm / ~1 inch)
Completed processor (Intel Core i7 Processor in this case). A microprocessor is the most complex manufactured product on earth. In fact, it takes hundreds of steps –only the most important ones have been visualized in this picture story -in the world's cleanest environment (a microprocessor fab) to make microprocessors.

Class Testing

scale: package level (~20mm / ~1 inch)
During this final test the processors will be tested for their key characteristics (among the tested characteristics are power dissipation and maximum frequency).

Binning

scale: package level (~20mm / ~1 inch)
Based on the test result of class testing processors with the same capabilities are put into the same transporting trays.

Retail Package

scale: package level (~20mm / ~1 inch)
The readily manufactured and tested processors (again Intel Core i7 Processor is shown here) either go to system manufacturers in trays or into retail stores in a box such as that shown here.
Images and explanatory text credit: Intel.